DDR2 ECC, combined with an integrated ECC memory controller, corrects many soft and hard single-bit memory errors, and minimizes disruption of service to LAN clients. Chipkill distributes information covered by error correction coding across separate memory chips so if any of the chips fail, the data can still be reconstructed from the remaining chips and the system can continue running. Increased processor performance coupled with DDR memory enables you to retrieve and process information faster and more efficiently. DDR memory execute twice the number of operations per cycle than traditional SDRAM memory, effectively doubling the data exchange rate between memory and processors.

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